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74V2G00
DUAL 2-INPUT NAND GATE
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HIGH SPEED: tPD = 3.7 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 1 A (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V IMPROVED LATCH-UP IMMUNITY
SOT23-8L
ORDER CODES PACKAGE SOT23-8L T UBE T&R 74V2G00STR
DESCRIPTION The 74V2G00 is an advanced high-speed CMOS DUAL 2-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal
wiring C2MOS technology. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 2000
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74V2G00
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 5 2, 6 7, 3 4 8 SYMBOL 1A, 2A 1B, 2B 1Y, 2Y GND VCC NAME AND FUNCT ION Data Input Data Input Data Output Ground (0V) Positive Supply Voltage
TRUTH TABLE
A L L H H B L H L H Y H H H L
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 260 Unit V V V V mA mA mA mA
o o
ICC or IGND DC VCC or Ground Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. 1) VCC =0V 2) High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 3.3 0.3V) (V CC = 5.0 0.5V) Parameter Valu e 2.0 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 100 0 to 20 Unit V V V V
o
C
ns/V ns/V
1) VCC =0V 2) High or Low State 3) VIN from 30% to70%of VCC
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DC SPECIFICATIONS
Symb ol Parameter T est Cond ition s V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 II ICC IOPD Input Leakage Current Quiescent Supply Current Output Leakage Current 0 to 5.5 5.5 0 I O =-50 A IO=-50 A IO=-50 A IO=-4 mA IO=-8 mA I O=50 A IO=50 A IO=50 A IO=4 mA IO=8 mA VI = 5.5V or GND VI = VCC or GND VOUT = 5.5V 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 1 0.5 2.0 3.0 4.5 Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 1.0 10 5.0 A A A V V Typ . Value T A = 25 o C Max. -40 to 85 o C Min . 1.5 0.7VCC 0.5 0.3VCC Max. V V Un it
AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time Test Co ndition CL (pF ) 15 50 15 50 Value T A = 25 o C Min. Typ . Max. 5.5 8.0 3.7 5.2 7.9 11.4 5.5 7.5 Un it -40 to 85 o C Min . Max. 1.0 1.0 1.0 1.0 9.5 13.0 6.5 8.5 ns
3.3(*) 3.3(*) 5.0(**) 5.0(**)
(*) Voltage range is 3.3V 0.3V (**) Voltage range is 5V 0.5V
CAPACITIVE CHARACTERISTICS
Symb ol Parameter T est Cond ition s
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Value T A = 25 C Min. Typ . 4 19 Max. 10 -40 to 85 C Min . Max. 10
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Un it
C IN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
pF pF
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/2
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74V2G00
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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SOT23-8L MECHANICAL DATA
mm MIN. A A1 A2 b C D E E1 L e e1 0.90 0.00 0.90 0.22 0.09 2.80 2.60 1.50 0.35 0.65 1.95 TYP. MAX. 1.45 0.15 1.30 0.38 0.20 3.00 3.00 1.75 0.55 MIN. 35.4 0.0 35.4 8.6 3.5 110.2 102.3 59.0 13.8 25.6 76.7 mils TYP. MAX. 57.1 5.9 51.2 14.9 7.8 118.1 118.1 68.8 21.6
DIM.
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74V2G00
Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com .
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